CMOS Manchester-carry-chain circuit as shown in FIG. 1 based on pass transistors and dynamic logic techniques have been used to implement arithmetic circuit N. H. E. Weste and K. Eshraghian, "Principles of CMOS VLSI Design," Addison Wesley: New York, N.Y., 1985; J. Kernhof, M. A. Beunder, B. Hoefflinger, and W. Haas, "High-Speed CMOS Adder and Multiplier Modules for Digital Signal Processing in a Semicustom Environment," IEEE J. Solid-State Circuits, pp. 570-575, June 1989; J. B. Kuo H. J. Liao and H. P. Chen, "A BiCMOS Dynamic Carry-Look-Ahead Adder Circuit for VLSI Implementation of High Speed Arithmetic Unit," IEEE J. Solid-State Circuits, March 1993; and J. B. Kuo, S. S. Chen, C. S. Chang, K. W. Su, and J. H. Lou, "A 1.5 V BiCMOS Dynamic Logic Circuit Using a "BiPMOS Pull-Down" Structure for VLSI Implementation of Full Adders," IEEE Trans. Circuits and Systems-I, Vol. 41, No. 4, pp. 329-332, April 1994!. The Manchester-carry-chain circuit is used to process the propagate (P.sub.i) and generate (G.sub.i) signals produced by the half adders to generate the carry signals (C.sub.i ), wherein a clock signal (CK) is required for the processing. With the pass transistor configuration, Manchester-carry-chain circuit has the smallest transistor count among all carry-chain circuits including domino and other static techniques introduced in the above-mentioned prior art references. The function of the Manchester-carry-chain circuit is: EQU C.sub.i =G.sub.i +C.sub.i-1 .multidot.P.sub.i,
wherein i=1.about.n, where n is the bit number; C.sub.i is an inverted carry signal; G.sub.i and P.sub.i are the generate and propagate signals (G.sub.i =X.sub.i .multidot.Y.sub.i, P.sub.I =X.sub.i .sym.Y.sub.i) produced from two inputs (X.sub.i, Y.sub.i) to the half adder. In the Manchester-carry-chain circuit, each bit carry signal (C.sub.i ) is low if the generate signal (G.sub.i) is high or if the propagate signal (P.sub.i) is high and the carry signal of the previous bit (C.sub.i-1 ) is low. Pass transistors have been used to control the operation of the Manchester-carry-chain circuit. However, when the Manchester-carry-chain chain is long, as in a 64-bit adder, the ripple-carry propagation delay becomes unacceptable due to the RC delay of the pass transistor. In other words, the density advantage of the Manchester-carry-chain circuit is offset by the drawback in the speed. This is especially serious when the supply voltage is scaled down, which is a trend for deep-submicron VLSI.